Modulation is the process of varying a carrier signal according to the pattern provided by another signal. In the field of data communications, modulators convert digital signals into analog signals suitable for transmission by using the digital signal as a pattern that determines the wave shape that the analog signal (i.e. the carrier signal) will have.
Pulse shaping networks have been used in modulators to convert an incoming digital data stream into a plurality of in-phase data streams and a plurality of quadrature-phase data streams. FIG. 1 shows an exemplary prior art modulator that includes a pulse shaping network. In this prior art example, the pulse shaping network is implemented in a single CMOS application specific integrated circuit (ASIC) and produces four in-phase data streams and four quadrature-phase data streams. Each of these data streams is formed by a string of ten bit digital samples that are output at a baud rate that may be as high as 68 megabaud. The digital samples of the in-phase data streams are then input into a multiplexer which operates at a rate equal to the number of digital samples per symbol times the baud rate and sequentially routes the samples into a digital to analog converter (DAC) to produce an I channel analog output. Likewise, a similar circuit produces the Q channel output.
However, this prior art implementation is undesirable because the multiplexer and DAC must operate at a rate substantially higher than the baud rate (i.e. up to 272 megabaud). The prior art solution implements the multiplexer and DAC in emitter coupled logic (ECL) or a similar technology to accommodate this higher operating rate. However, although ECL components are fast, they are also power hungry and expensive parts. Unfortunately, this approach is undesirable in systems which are battery powered and/or operate in space because these types of components typically consume significantly more power.
Another undesirable aspect of this prior art modulator is that the pulse shaping network produces a number of output samples per symbol each having a ten bit resolution. As a result, the digital to analog converts must have at least a ten bit resolution. The higher bit resolution of the DACs results in a slower processing time unless higher speed, more costly DACs are utilized. Additionally, another problem exists in this prior art solution in that there are eight of these ten bit output samples per symbol. Eighty pins are needed for their outputs alone, resulting in a complex ASIC package for the pulse shaping network.
There is a continual need for developing ways to decrease the size of equipment without decreasing capability. This need for smaller equipment and associated components arises from applications where portability is required, where there may be limited space for equipment, and/or where cost is an important factor. An efficient approach for implementing a modulator system in a limited space is to incorporate a pulse shaping network and DACs in a common ASIC. This approach would have an additional benefit in that by incorporating the system on a common semiconductor substrate, the DACs would be very well matched. Well matched circuitry may prevent differential temperature drift problems. Unfortunately, the prior art modulator cannot accommodate this efficiency because the high precision, high speed DACs are incompatible with the ASIC technology.